import java.io.FileNotFoundException;
import java.io.FileOutputStream;
import java.io.FileWriter;
import java.io.IOException;

import javax.swing.JOptionPane;

/*
 * This java class file generates the verilog file according to the input arguments entered in
 * the GUI forms
 * 
 */

public class Verilog_Main_File_Generator
{

	
	public static void main(String args[]) throws IOException
	{
		String file_path = "C:/Users/kspatel/workspace/ISS_SIMD_Project/src/verilog_test.v";
		try {
			FileWriter verilog_main_out  = new FileWriter (file_path);
			String temp_string = "Jai Sairam";
			/*
			 *  Writing name of the module with ports names; 
			 *  Input ports are first in the list 
			 */
			
			// Writing  the name of header file included
			
			verilog_main_out.write(temp_string + "\n");
			verilog_main_out.write("Jai Matapita");
			
			// Declaring Parameters
			
			//Declaring input ports
			
			
			//Declaring output ports
			
			
			/*****Declaring registers*****/
			
				//Input registers
			
			
				//Output Registers
			
			
			//Declaring wires
			
			
			//Declaring clock
			
			//Opcode decoding logic
			
			/*
			 * Connect the CFUs as per the selection in the GUI;
			 * Default: Cross
			 */
			System.out.println(HDL_Coder_Form.hdl_coder_connection_type);
			if ((HDL_Coder_Form.hdl_coder_connection_type.compareToIgnoreCase("Star")) == 0)
			{
				verilog_main_out.write("Star\n");

			}
			if(HDL_Coder_Form.hdl_coder_connection_type.compareToIgnoreCase("Cross") == 0)
			{
				verilog_main_out.write("Cross\n");
			}
				
			verilog_main_out.close();
			
		} catch (FileNotFoundException e) {
			// TODO Auto-generated catch block
			e.printStackTrace();
			System.out.println("File not found exception: " + e );
		}
		
				

		
		
		
	}
	
	
	
}